The use of configurable integrated circuits (“IC's”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that usually has logic circuits, interconnect circuits, and input/output (I/O) circuits. The logic circuits (also called logic blocks) are typically arranged as an internal array of circuits. These logic circuits are connected together through numerous interconnect circuits (also called interconnects). The logic and interconnect circuits are typically surrounded by the I/O circuits.
FIG. 1 illustrates an example of a configurable logic circuit 100. This logic circuit can be configured to perform a number of different functions. As shown in FIG. 1, the logic circuit 100 receives a set of input data 105 and a set of configuration data 110. The configuration data set can be stored in a set of SRAM cells 115. From the set of functions that the logic circuit 100 can perform, the configuration data set specifies a particular function that this circuit is to perform on the input data set. Once the logic circuit performs its function on the input data set, it provides the output of this function on a set of output lines 120. The logic circuit 100 is said to be configurable, as the configuration data set “configures” the logic circuit to perform a particular function, and this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers and look-up tables are two examples of configurable logic circuits.
FIG. 2 illustrates an example of a configurable interconnect circuit 200. This interconnect circuit 200 connects a set of input data 205 to a set of output data 210. This circuit receives configuration data bits 215 that are stored in a set of SRAM cells 220. The configuration bits specify how the interconnect circuit should connect the input data set to the output data set. The interconnect circuit 200 is said to be configurable, as the configuration data set “configures” the interconnect circuit to use a particular connection scheme that connects the input data set to the output data set in a desired manner. Moreover, this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers are one example of interconnect circuits.
FIG. 3 illustrates a portion of a prior art configurable IC 300. As shown in this figure, the IC 300 includes an array of configurable logic circuits 305 and configurable interconnect circuits 310. The IC 300 has two types of interconnect circuits 310a and 310b. Interconnect circuits 310a connect interconnect circuits 310b and logic circuits 305, while interconnect circuits 310b connect interconnect circuits 310a to other interconnect circuits 310a. In some cases, the IC 300 includes hundreds or thousands of logic circuits 305 and interconnect circuits 310.
In some configurable IC architectures, an interconnect circuit 310b can connect to interconnect circuits 310b that are several columns or several rows away from it in the array. FIG. 4 illustrates several such connections in a prior configurable IC architecture 400. In the architecture 400, each logic circuit 305 forms a configurable computational tile 405 in conjunction with two neighboring interconnect circuits 310a and one neighboring interconnect circuit 310b. In each particular tile, each interconnect circuit 310a can receive inputs from the interconnect circuit 310b in the tile and supply a sub-set of the received input signals (e.g., one input signal) to the logic circuit 305 of the tile.
The interconnect circuits 310b in each particular tile serve as switchboxes that connect to other interconnect circuits 310b through intervening interconnect circuits 310a. As shown in FIG. 4, these switchboxes 310b can also connect to other switchboxes 310b that are two or more rows or columns away but in the same column or row. For instance, each switchbox can connect to switchboxes that are one, two, three and six rows above and below it, and to switchboxes that are one, two, three, and six columns to its right and left.
In the architecture of FIG. 4, a particular logic circuit 305 connects to logic circuits that are in the four tiles that are diagonally adjacent to the particular logic circuit's tile, through four connection boxes 310a in these tiles. For instance, FIG. 4 illustrates that the logic circuit 305 in tile 405a connects to the logic circuits 305 in tiles 405b–e through a connection box 310a in these tiles.
The advantage of the connection architecture illustrated in FIG. 4 is that it allows one computation tile to connect to another computational tile that is not a neighboring tile. On the other hand, this architecture requires the use of multiple connections to connect two tiles that are not diagonally adjacent and that are in two different rows and columns. This requirement makes the connection architecture illustrated in FIG. 4 inefficient and expensive as each connection requires the use of transistor switching logic.
Also, the connection architecture illustrated in FIG. 4 employs the same set of long connection schemes for each tile. Hence, as shown in FIG. 5, this architecture can result in a loop between two tiles 505 and 510 in the same column, or two tiles 515 and 520 in the same row. Such cycles are undesirable as they come at the expense of reachability of other tiles. The uniform connection architecture of FIG. 4 is also inefficient as it provides more ways than necessary for reaching one tile from another tile. This redundancy is illustrated in FIG. 5, which illustrates that the tile 525 can connect to tile 530 through two different sets of connections, one that goes through tile 535 and one that goes through tile 540. This redundancy is undesirable as it comes at the expense of reachability of other tiles.
Therefore, there is a need in the art for a configurable IC that has a wiring architecture that increases the interconnectivity between its configurable circuits.